347 lines
12 KiB
PHP
347 lines
12 KiB
PHP
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/* Name: usbdrvasm16.inc
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* Project: V-USB, virtual USB port for Atmel's(r) AVR(r) microcontrollers
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* Author: Christian Starkjohann
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* Creation Date: 2007-06-15
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* Tabsize: 4
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* Copyright: (c) 2007 by OBJECTIVE DEVELOPMENT Software GmbH
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* License: GNU GPL v2 (see License.txt), GNU GPL v3 or proprietary (CommercialLicense.txt)
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* Revision: $Id: usbdrvasm16.inc 760 2009-08-09 18:59:43Z cs $
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*/
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/* Do not link this file! Link usbdrvasm.S instead, which includes the
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* appropriate implementation!
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*/
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/*
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General Description:
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This file is the 16 MHz version of the asssembler part of the USB driver. It
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requires a 16 MHz crystal (not a ceramic resonator and not a calibrated RC
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oscillator).
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See usbdrv.h for a description of the entire driver.
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Since almost all of this code is timing critical, don't change unless you
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really know what you are doing! Many parts require not only a maximum number
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of CPU cycles, but even an exact number of cycles!
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*/
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;max stack usage: [ret(2), YL, SREG, YH, bitcnt, shift, x1, x2, x3, x4, cnt] = 12 bytes
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;nominal frequency: 16 MHz -> 10.6666666 cycles per bit, 85.333333333 cycles per byte
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; Numbers in brackets are clocks counted from center of last sync bit
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; when instruction starts
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USB_INTR_VECTOR:
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;order of registers pushed: YL, SREG YH, [sofError], bitcnt, shift, x1, x2, x3, x4, cnt
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push YL ;[-25] push only what is necessary to sync with edge ASAP
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in YL, SREG ;[-23]
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push YL ;[-22]
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push YH ;[-20]
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;----------------------------------------------------------------------------
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; Synchronize with sync pattern:
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;----------------------------------------------------------------------------
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;sync byte (D-) pattern LSb to MSb: 01010100 [1 = idle = J, 0 = K]
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;sync up with J to K edge during sync pattern -- use fastest possible loops
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;The first part waits at most 1 bit long since we must be in sync pattern.
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;YL is guarenteed to be < 0x80 because I flag is clear. When we jump to
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;waitForJ, ensure that this prerequisite is met.
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waitForJ:
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inc YL
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sbis USBIN, USBMINUS
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brne waitForJ ; just make sure we have ANY timeout
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waitForK:
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;The following code results in a sampling window of < 1/4 bit which meets the spec.
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sbis USBIN, USBMINUS ;[-15]
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rjmp foundK ;[-14]
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sbis USBIN, USBMINUS
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rjmp foundK
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sbis USBIN, USBMINUS
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rjmp foundK
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sbis USBIN, USBMINUS
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rjmp foundK
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sbis USBIN, USBMINUS
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rjmp foundK
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sbis USBIN, USBMINUS
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rjmp foundK
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#if USB_COUNT_SOF
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lds YL, usbSofCount
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inc YL
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sts usbSofCount, YL
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#endif /* USB_COUNT_SOF */
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#ifdef USB_SOF_HOOK
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USB_SOF_HOOK
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#endif
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rjmp sofError
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foundK: ;[-12]
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;{3, 5} after falling D- edge, average delay: 4 cycles [we want 5 for center sampling]
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;we have 1 bit time for setup purposes, then sample again. Numbers in brackets
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;are cycles from center of first sync (double K) bit after the instruction
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push bitcnt ;[-12]
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; [---] ;[-11]
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lds YL, usbInputBufOffset;[-10]
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; [---] ;[-9]
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clr YH ;[-8]
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subi YL, lo8(-(usbRxBuf));[-7] [rx loop init]
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sbci YH, hi8(-(usbRxBuf));[-6] [rx loop init]
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push shift ;[-5]
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; [---] ;[-4]
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ldi bitcnt, 0x55 ;[-3] [rx loop init]
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sbis USBIN, USBMINUS ;[-2] we want two bits K (sample 2 cycles too early)
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rjmp haveTwoBitsK ;[-1]
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pop shift ;[0] undo the push from before
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pop bitcnt ;[2] undo the push from before
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rjmp waitForK ;[4] this was not the end of sync, retry
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; The entire loop from waitForK until rjmp waitForK above must not exceed two
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; bit times (= 21 cycles).
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;----------------------------------------------------------------------------
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; push more registers and initialize values while we sample the first bits:
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;----------------------------------------------------------------------------
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haveTwoBitsK:
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push x1 ;[1]
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push x2 ;[3]
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push x3 ;[5]
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ldi shift, 0 ;[7]
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ldi x3, 1<<4 ;[8] [rx loop init] first sample is inverse bit, compensate that
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push x4 ;[9] == leap
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in x1, USBIN ;[11] <-- sample bit 0
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andi x1, USBMASK ;[12]
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bst x1, USBMINUS ;[13]
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bld shift, 7 ;[14]
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push cnt ;[15]
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ldi leap, 0 ;[17] [rx loop init]
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ldi cnt, USB_BUFSIZE;[18] [rx loop init]
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rjmp rxbit1 ;[19] arrives at [21]
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;----------------------------------------------------------------------------
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; Receiver loop (numbers in brackets are cycles within byte after instr)
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;----------------------------------------------------------------------------
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; duration of unstuffing code should be 10.66666667 cycles. We adjust "leap"
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; accordingly to approximate this value in the long run.
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unstuff6:
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andi x2, USBMASK ;[03]
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ori x3, 1<<6 ;[04] will not be shifted any more
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andi shift, ~0x80;[05]
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mov x1, x2 ;[06] sampled bit 7 is actually re-sampled bit 6
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subi leap, -1 ;[07] total duration = 11 bits -> subtract 1/3
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rjmp didUnstuff6 ;[08]
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unstuff7:
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ori x3, 1<<7 ;[09] will not be shifted any more
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in x2, USBIN ;[00] [10] re-sample bit 7
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andi x2, USBMASK ;[01]
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andi shift, ~0x80;[02]
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subi leap, 2 ;[03] total duration = 10 bits -> add 1/3
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rjmp didUnstuff7 ;[04]
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unstuffEven:
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ori x3, 1<<6 ;[09] will be shifted right 6 times for bit 0
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in x1, USBIN ;[00] [10]
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andi shift, ~0x80;[01]
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andi x1, USBMASK ;[02]
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breq se0 ;[03]
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subi leap, -1 ;[04] total duration = 11 bits -> subtract 1/3
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nop2 ;[05]
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rjmp didUnstuffE ;[06]
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unstuffOdd:
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ori x3, 1<<5 ;[09] will be shifted right 4 times for bit 1
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in x2, USBIN ;[00] [10]
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andi shift, ~0x80;[01]
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andi x2, USBMASK ;[02]
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breq se0 ;[03]
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subi leap, -1 ;[04] total duration = 11 bits -> subtract 1/3
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nop2 ;[05]
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rjmp didUnstuffO ;[06]
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rxByteLoop:
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andi x1, USBMASK ;[03]
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eor x2, x1 ;[04]
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subi leap, 1 ;[05]
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brpl skipLeap ;[06]
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subi leap, -3 ;1 one leap cycle every 3rd byte -> 85 + 1/3 cycles per byte
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nop ;1
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skipLeap:
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subi x2, 1 ;[08]
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ror shift ;[09]
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didUnstuff6:
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cpi shift, 0xfc ;[10]
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in x2, USBIN ;[00] [11] <-- sample bit 7
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brcc unstuff6 ;[01]
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andi x2, USBMASK ;[02]
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eor x1, x2 ;[03]
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subi x1, 1 ;[04]
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ror shift ;[05]
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didUnstuff7:
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cpi shift, 0xfc ;[06]
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brcc unstuff7 ;[07]
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eor x3, shift ;[08] reconstruct: x3 is 1 at bit locations we changed, 0 at others
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st y+, x3 ;[09] store data
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rxBitLoop:
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in x1, USBIN ;[00] [11] <-- sample bit 0/2/4
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andi x1, USBMASK ;[01]
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eor x2, x1 ;[02]
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andi x3, 0x3f ;[03] topmost two bits reserved for 6 and 7
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subi x2, 1 ;[04]
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ror shift ;[05]
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cpi shift, 0xfc ;[06]
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brcc unstuffEven ;[07]
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didUnstuffE:
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lsr x3 ;[08]
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lsr x3 ;[09]
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rxbit1:
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in x2, USBIN ;[00] [10] <-- sample bit 1/3/5
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andi x2, USBMASK ;[01]
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breq se0 ;[02]
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eor x1, x2 ;[03]
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subi x1, 1 ;[04]
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ror shift ;[05]
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cpi shift, 0xfc ;[06]
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brcc unstuffOdd ;[07]
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didUnstuffO:
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subi bitcnt, 0xab;[08] == addi 0x55, 0x55 = 0x100/3
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brcs rxBitLoop ;[09]
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subi cnt, 1 ;[10]
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in x1, USBIN ;[00] [11] <-- sample bit 6
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brcc rxByteLoop ;[01]
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rjmp overflow
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macro POP_STANDARD ; 14 cycles
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pop cnt
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pop x4
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pop x3
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pop x2
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pop x1
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pop shift
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pop bitcnt
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endm
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macro POP_RETI ; 7 cycles
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pop YH
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pop YL
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out SREG, YL
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pop YL
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endm
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#include "asmcommon.inc"
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; USB spec says:
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; idle = J
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; J = (D+ = 0), (D- = 1)
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; K = (D+ = 1), (D- = 0)
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; Spec allows 7.5 bit times from EOP to SOP for replies
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bitstuffN:
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eor x1, x4 ;[5]
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ldi x2, 0 ;[6]
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nop2 ;[7]
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nop ;[9]
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out USBOUT, x1 ;[10] <-- out
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rjmp didStuffN ;[0]
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bitstuff6:
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eor x1, x4 ;[5]
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ldi x2, 0 ;[6] Carry is zero due to brcc
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rol shift ;[7] compensate for ror shift at branch destination
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rjmp didStuff6 ;[8]
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bitstuff7:
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ldi x2, 0 ;[2] Carry is zero due to brcc
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rjmp didStuff7 ;[3]
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sendNakAndReti:
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ldi x3, USBPID_NAK ;[-18]
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rjmp sendX3AndReti ;[-17]
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sendAckAndReti:
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ldi cnt, USBPID_ACK ;[-17]
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sendCntAndReti:
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mov x3, cnt ;[-16]
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sendX3AndReti:
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ldi YL, 20 ;[-15] x3==r20 address is 20
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ldi YH, 0 ;[-14]
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ldi cnt, 2 ;[-13]
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; rjmp usbSendAndReti fallthrough
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;usbSend:
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;pointer to data in 'Y'
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;number of bytes in 'cnt' -- including sync byte [range 2 ... 12]
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;uses: x1...x4, btcnt, shift, cnt, Y
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;Numbers in brackets are time since first bit of sync pattern is sent
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;We don't match the transfer rate exactly (don't insert leap cycles every third
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;byte) because the spec demands only 1.5% precision anyway.
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usbSendAndReti: ; 12 cycles until SOP
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in x2, USBDDR ;[-12]
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ori x2, USBMASK ;[-11]
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sbi USBOUT, USBMINUS;[-10] prepare idle state; D+ and D- must have been 0 (no pullups)
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in x1, USBOUT ;[-8] port mirror for tx loop
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out USBDDR, x2 ;[-7] <- acquire bus
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; need not init x2 (bitstuff history) because sync starts with 0
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ldi x4, USBMASK ;[-6] exor mask
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ldi shift, 0x80 ;[-5] sync byte is first byte sent
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txByteLoop:
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ldi bitcnt, 0x35 ;[-4] [6] binary 0011 0101
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txBitLoop:
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sbrs shift, 0 ;[-3] [7]
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eor x1, x4 ;[-2] [8]
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out USBOUT, x1 ;[-1] [9] <-- out N
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ror shift ;[0] [10]
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ror x2 ;[1]
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didStuffN:
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cpi x2, 0xfc ;[2]
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brcc bitstuffN ;[3]
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lsr bitcnt ;[4]
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brcc txBitLoop ;[5]
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brne txBitLoop ;[6]
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sbrs shift, 0 ;[7]
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eor x1, x4 ;[8]
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didStuff6:
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out USBOUT, x1 ;[-1] [9] <-- out 6
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ror shift ;[0] [10]
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ror x2 ;[1]
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cpi x2, 0xfc ;[2]
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brcc bitstuff6 ;[3]
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ror shift ;[4]
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didStuff7:
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ror x2 ;[5]
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sbrs x2, 7 ;[6]
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eor x1, x4 ;[7]
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nop ;[8]
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cpi x2, 0xfc ;[9]
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out USBOUT, x1 ;[-1][10] <-- out 7
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brcc bitstuff7 ;[0] [11]
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ld shift, y+ ;[1]
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dec cnt ;[3]
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brne txByteLoop ;[4]
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;make SE0:
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cbr x1, USBMASK ;[5] prepare SE0 [spec says EOP may be 21 to 25 cycles]
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lds x2, usbNewDeviceAddr;[6]
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lsl x2 ;[8] we compare with left shifted address
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subi YL, 20 + 2 ;[9] Only assign address on data packets, not ACK/NAK in x3
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sbci YH, 0 ;[10]
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out USBOUT, x1 ;[11] <-- out SE0 -- from now 2 bits = 22 cycles until bus idle
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;2006-03-06: moved transfer of new address to usbDeviceAddr from C-Code to asm:
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;set address only after data packet was sent, not after handshake
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breq skipAddrAssign ;[0]
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sts usbDeviceAddr, x2; if not skipped: SE0 is one cycle longer
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skipAddrAssign:
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;end of usbDeviceAddress transfer
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ldi x2, 1<<USB_INTR_PENDING_BIT;[2] int0 occurred during TX -- clear pending flag
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USB_STORE_PENDING(x2) ;[3]
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ori x1, USBIDLE ;[4]
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in x2, USBDDR ;[5]
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cbr x2, USBMASK ;[6] set both pins to input
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mov x3, x1 ;[7]
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cbr x3, USBMASK ;[8] configure no pullup on both pins
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ldi x4, 4 ;[9]
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|
|
se0Delay:
|
||
|
|
dec x4 ;[10] [13] [16] [19]
|
||
|
|
brne se0Delay ;[11] [14] [17] [20]
|
||
|
|
out USBOUT, x1 ;[21] <-- out J (idle) -- end of SE0 (EOP signal)
|
||
|
|
out USBDDR, x2 ;[22] <-- release bus now
|
||
|
|
out USBOUT, x3 ;[23] <-- ensure no pull-up resistors are active
|
||
|
|
rjmp doReturn
|