385 lines
12 KiB
C
385 lines
12 KiB
C
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// Pi1541 - A Commodore 1541 disk drive emulator
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// Copyright(C) 2018 Stephen White
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//
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// This file is part of Pi1541.
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//
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// Pi1541 is free software : you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// Pi1541 is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with Pi1541. If not, see <http://www.gnu.org/licenses/>.
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#ifndef M6522_H
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#define M6522_H
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#include "IOPort.h"
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#include "m6502.h"
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class m6522
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{
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// $1800
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// PB 0 data in
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// PB 1 data out
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// PB 2 clock in
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// PB 3 clock out
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// PB 4 ATNA
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// PB 5,6 device address
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// PB 7,CA1 ATN IN
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// $1C00
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// PB 0,1 step motor
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// PB 2 MTR dirve motor
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// PB 3 ACT drive LED
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// PB 4 WPS write protect switch
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// PB 5,6 bit rate
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// PB 7 Sync
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// CA 1 Byte ready
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// CA 2 SOE set overflow enable 6502
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// CB 2 read/write
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// IFR
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//REG 13 -- INTERRUPT FLAG REGISTER
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//+-+-+-+-+-+-+-+-+
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//|7|6|5|4|3|2|1|0| SET BY CLEARED BY
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//+-+-+-+-+-+-+-+-+ +-----------------------+------------------------------+
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// | | | | | | | +--CA2| CA2 ACTIVE EDGE | READ OR WRITE REG 1 (ORA)* |
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// | | | | | | | +-----------------------+------------------------------+
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// | | | | | | +--CA1--| CA1 ACTIVE EDGE | READ OR WRITE REG 1 (ORA) |
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// | | | | | | +-----------------------+------------------------------+
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// | | | | | +SHIFT REG| COMPLETE 8 SHIFTS | READ OR WRITE SHIFT REG |
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// | | | | | +-----------------------+------------------------------+
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// | | | | +-CB2-------| CB2 ACTIVE EDGE | READ OR WRITE ORB* |
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// | | | | +-----------------------+------------------------------+
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// | | | +-CB1---------| CB1 ACTIVE EDGE | READ OR WRITE ORB |
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// | | | +-----------------------+------------------------------+
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// | | +-TIMER 2-------| TIME-OUT OF T2 | READ T2 LOW OR WRITE T2 HIGH |
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// | | +-----------------------+------------------------------+
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// | +-TIMER 1---------| TIME-OUT OF T1 | READ T1 LOW OR WRITE T1 HIGH |
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// | +-----------------------+------------------------------+
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// +-IRQ---------------| ANY ENABLED INTERRUPT | CLEAR ALL INTERRUPTS |
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// +-----------------------+------------------------------+
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enum Registers
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{
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ORB, // 0 Port B
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ORA, // 1 Port A
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DDRB, // 2 Data direction register for port B
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DDRA, // 3 Data direction register for port A
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T1CL, // 4 Timer 1 count low
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T1CH, // 5 Timer 1 count high
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T1LL, // 6 Timer 1 latch low
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T1LH, // 7 Timer 1 latch high
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T2CL, // 8 Timer 2 count low read-only
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T2LL = T2CL, // 8 Timer 2 latch low write-only
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T2CH, // 9 Timer 2 count high read/write
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SR, // 10 Serial port shift register
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ACR, // 11 Auxiliary control register
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FCR, // 12 Peripheral control register
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IFR, // 13 Interrupt flag register
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IER, // 14 Interrupt Enable Register
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ORA_NH // 15 Port A with no handshake
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};
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enum ACR
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{
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ACR_PA_LATCH_ENABLE = 0x01, // Port A latch
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// 0 = disabled
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// 1 = enabled on CA1 transition (in)
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ACR_PB_LATCH_ENABLE = 0x02, // Port B latch
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// 0 = disabled
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// 1 = enabled on CB1 transition (in/out)
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ACR_SHIFTREG_CTRL = 0x1c, // Shift register control
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// 000 = shift reg disabled
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// 001 = shift in by timer 2
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// 010 = shift in by phi2
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// 011 = shift in by external clock (PB6?)
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// 100 = free run shift out by timer 2 (keep shifting the same byte out over and over)
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// 101 = shift out by timer 2
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// 110 = shift out by phi2
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// 111 = shift out by external clock(PB6 ? )
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ACR_T2_MODE = 0x20, // Timer 2 control
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// 0 = one shot (timed interrrupt)
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// 1 = count down with pulses on PB6
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ACR_T1_MODE = 0x40, // Timer 1 control
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// 0 = one shot
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// 1 = continuous, i.e. on underflow timer restarts at latch value.
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ACR_T1_OUT_PB7 = 0x80 // Output on PB7
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};
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enum IR
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{
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IR_CA2 = 0x01, // CA2 flag
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// Cleared by a read or write of ORA
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IR_CA1 = 0x02, // CA1 flag
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// Cleared by a read or write of ORA
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IR_SR = 0x04, // Shift Register completion
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// 1 at end of 8 shifts
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// Cleared by read or write of SR
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IR_CB2 = 0x08, // CB2 flag
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// Cleared by a read or write of ORB
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IR_CB1 = 0x10, // CB1 flag
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// Cleared by a read or write of ORB
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IR_T2 = 0x20, // Timer 2
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// 1 when time out
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// 0 after reading T2 low-byte counter or writing T2 high-byte counter
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IR_T1 = 0x40, // Timer 1
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// 1 when time out
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// 0 after reading T1 low-byte counter or writing T1 high-byte latch
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IR_IRQ = 0x80 // General interrupt status bit
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// 1 if any interrupt active and enabled
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// 0 when interrupt condition cleared
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};
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public:
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/*
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FCR/PCR
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+---+---+---+---+---+---+---+---+
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
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+---+---+---+---+---+---+---+---+
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+----+----+ | +----+----+ |
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CB2 CONTROL -----+ | | +- CA1 INTERRUPT CONTROL
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+-+-+-+------------------------+ | | +--------------------------+
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|7|6|5| OPERATION | | | | 0 = NEGATIVE ACTIVE EDGE |
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+-+-+-+------------------------+ | | | 1 = POSITIVE ACTIVE EDGE |
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|0|0|0| INPUT NEG. ACTIVE EDGE | | | +--------------------------+
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+-+-+-+------------------------+ | +---- CA2 INTERRUPT CONTROL
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|0|0|1| INDEPENDENT INTERRUPT | | +-+-+-+------------------------+
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| | | | INPUT NEGATIVE EDGE | | |3|2|1| OPERATION |
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+-+-+-+------------------------+ | +-+-+-+------------------------+
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|0|1|0| INPUT POS. ACTIVE EDGE | | |0|0|0| INPUT NEG. ACTIVE EDGE |
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+-+-+-+------------------------+ | +-+-+-+------------------------+
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|0|1|1| INDEPENDENT INTERRUPT | | |0|0|1| INDEPENDENT INTERRUPT |
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| | | | INPUT POSITIVE EDGE | | | | | | INPUT NEGATIVE EDGE |
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+-+-+-+------------------------+ | +-+-+-+------------------------+
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|1|0|0| HANDSHAKE OUTPUT | | |0|1|0| INPUT POS. ACTIVE EDGE |
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+-+-+-+------------------------+ | +-+-+-+------------------------+
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|1|0|1| PULSE OUTPUT | | |0|1|1| INDEPENDENT INTERRUPT |
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+-+-+-+------------------------+ | | | | | INPUT POSITIVE EDGE |
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|1|1|0| LOW OUTPUT | | +-+-+-+------------------------+
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+-+-+-+------------------------+ | |1|0|0| HANDSHAKE OUTPUT |
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|1|1|1| HIGH OUTPUT | | +-+-+-+------------------------+
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+-+-+-+------------------------+ | |1|0|1| PULSE OUTPUT |
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CB1 INTERRUPT CONTROL --------+ +-+-+-+------------------------+
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+--------------------------+ |1|1|0| LOW OUTPUT |
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| 0 = NEGATIVE ACTIVE EDGE | +-+-+-+------------------------+
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| 1 = POSITIVE ACTIVE EDGE | |1|1|1| HIGH OUTPUT |
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+--------------------------+ +-+-+-+------------------------+
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*/
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enum FCR
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{
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FCR_CA1 = 0x01,
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FCR_CA2_OUTPUT_MODE0 = 0x02, // 1c00 byte ready active 1541 rom $FAC1
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FCR_CA2_OUTPUT_MODE1 = 0x04,
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FCR_CA2_EDGE_TRIGGER_MODE = 0x04,
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FCR_CA2_IO = 0x08,
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FCR_CA2 = 0x0e,
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FCR_CB1 = 0x01,
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FCR_CB2_OUTPUT_MODE0 = 0x20, // 1c00 writing
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FCR_CB2_OUTPUT_MODE1 = 0x40,
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FCR_CB2_EDGE_TRIGGER_MODE = 0x40,
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FCR_CB2_IO = 0x80,
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FCR_CB2 = 0xe0,
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};
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m6522();
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void Reset();
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void ConnectIRQ(Interrupt* irq) { this->irq = irq; }
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inline IOPort* GetPortA() { return &portA; }
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inline bool GetLatchPortA() const { return latchPortA; }
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inline unsigned char GetLatchedValueA() { return latchedValueA; }
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inline bool GetCA1() { return ca1; }
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void InputCA1(bool value);
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inline bool GetCA2() { return ca2; }
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void InputCA2(bool value);
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inline IOPort* GetPortB() { return &portB; }
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bool GetLatchPortB() const { return latchPortB; }
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unsigned char GetLatchedValueB() { return latchedValueB; }
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inline bool GetCB1() { return cb1; }
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void InputCB1(bool value);
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inline bool GetCB2() { return cb2; }
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void InputCB2(bool value);
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void Execute();
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unsigned char Read(unsigned int address);
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unsigned char Peek(unsigned int address);
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void Write(unsigned int address, unsigned char value);
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inline unsigned char GetFCR()
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{
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return functionControlRegister;
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}
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private:
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inline unsigned char ReadPortB()
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{
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unsigned char ddr = portB.GetDirection();
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unsigned char value = (latchPortB && (interruptFlagRegister & (unsigned char)IR_CB1) != 0) ? latchedValueB : (unsigned char)((portB.GetInput() & ~ddr) | (portB.GetOutput() & ddr));
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ClearInterrupt(IR_CB1 | IR_CB2);
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return value;
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}
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inline void WritePortB(unsigned char value)
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{
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ClearInterrupt(IR_CB1 | IR_CB2);
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if ((functionControlRegister & (unsigned char)(FCR_CB2_IO | FCR_CB2_OUTPUT_MODE1)) == (unsigned char)(FCR_CB2_IO | FCR_CB2_OUTPUT_MODE1))
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cb2 = false;
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portB.SetOutput(value);
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}
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inline unsigned char ReadPortA(bool handshake)
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{
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unsigned char ddr = portA.GetDirection();
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unsigned char value = (latchPortA && (interruptFlagRegister & (unsigned char)IR_CA1) != 0) ? latchedValueA : (unsigned char)((portA.GetInput() & ~ddr) | (portA.GetOutput() & ddr));
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if (handshake)
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ClearInterrupt(IR_CA1 | IR_CA2);
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return value;
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}
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inline unsigned char PeekPortA()
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{
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unsigned char ddr = portA.GetDirection();
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unsigned char value = (latchPortA && (interruptFlagRegister & (unsigned char)IR_CA1) != 0) ? latchedValueA : (unsigned char)((portA.GetInput() & ~ddr) | (portA.GetOutput() & ddr));
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return value;
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}
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inline void WritePortA(unsigned char value, bool handshake)
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{
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if (handshake)
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{
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ClearInterrupt(IR_CA1 | IR_CA2);
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if ((functionControlRegister & (unsigned char)(FCR_CA2_IO | FCR_CA2_OUTPUT_MODE1)) == (unsigned char)(FCR_CA2_IO | FCR_CA2_OUTPUT_MODE1))
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ca2 = false;
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}
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portA.SetOutput(value);
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}
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inline unsigned char PeekPortB()
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{
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unsigned char ddr = portB.GetDirection();
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unsigned char value = (latchPortB && (interruptFlagRegister & (unsigned char)IR_CB1) != 0) ? latchedValueB : (unsigned char)((portB.GetInput() & ~ddr) | (portB.GetOutput() & ddr));
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return value;
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}
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inline void SetInterrupt(unsigned char flag)
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{
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if (!(interruptFlagRegister & flag))
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{
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interruptFlagRegister |= flag;
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OutputIRQ();
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}
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}
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inline void ClearInterrupt(unsigned char flag)
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{
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if (interruptFlagRegister & flag)
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{
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interruptFlagRegister &= ~flag;
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OutputIRQ();
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}
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}
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inline void OutputIRQ()
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{
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if (interruptEnabledRegister & interruptFlagRegister & 0x7f)
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{
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if ((interruptFlagRegister & IR_IRQ) == 0)
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{
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interruptFlagRegister |= IR_IRQ;
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if (irq) irq->Assert();
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}
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}
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else
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{
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if (interruptFlagRegister & IR_IRQ)
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{
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interruptFlagRegister &= ~IR_IRQ;
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if (irq) irq->Release();
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}
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}
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}
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struct Counter
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{
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union
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{
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unsigned short value;
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struct
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{
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// if porting to big endian, swap these.
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unsigned char l;
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unsigned char h;
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} bytes;
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};
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};
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Interrupt* irq;
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unsigned char functionControlRegister;
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unsigned char auxiliaryControlRegister;
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IOPort portA;
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bool latchPortA;
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unsigned char latchedValueA;
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bool ca1;
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bool ca2;
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bool pulseCA2;
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IOPort portB;
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bool latchPortB;
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unsigned char latchedValueB;
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bool cb1;
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bool cb1Old;
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bool cb2;
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bool pulseCB2;
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Counter t1c;
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Counter t1l;
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bool t1Ticking;
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bool t1Reload;
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bool t1OutPB7;
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|
bool t1FreeRun;
|
||
|
|
bool t1FreeRunIRQsOn;
|
||
|
|
bool t1TimedOut;
|
||
|
|
bool t1_pb7;
|
||
|
|
bool t1OneShotTriggeredIRQ;
|
||
|
|
|
||
|
|
Counter t2c;
|
||
|
|
unsigned char t2Latch;
|
||
|
|
bool t2Reload;
|
||
|
|
bool t2CountingDown;
|
||
|
|
bool t2CountingPB6ModeOld;
|
||
|
|
bool t2CountingPB6Mode;
|
||
|
|
bool t2TimedOut;
|
||
|
|
bool t2LowTimedOut;
|
||
|
|
bool t2OneShotTriggeredIRQ;
|
||
|
|
unsigned t2TimedOutCount;
|
||
|
|
unsigned char pb6Old;
|
||
|
|
|
||
|
|
unsigned char interruptFlagRegister;
|
||
|
|
unsigned char interruptEnabledRegister;
|
||
|
|
|
||
|
|
unsigned char shiftRegister;
|
||
|
|
unsigned bitsShiftedSoFar;
|
||
|
|
unsigned cb1OutputShiftClock;
|
||
|
|
unsigned char cb2Shift; // version of cb2 controlled by the shift register
|
||
|
|
bool cb1OutputShiftClockPositiveEdge;
|
||
|
|
};
|
||
|
|
|
||
|
|
#endif
|