207 lines
7.2 KiB
C
207 lines
7.2 KiB
C
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// Pi1541 - A Commodore 1541 disk drive emulator
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// Copyright(C) 2018 Stephen White
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//
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// This file is part of Pi1541.
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//
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// Pi1541 is free software : you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// Pi1541 is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with Pi1541. If not, see <http://www.gnu.org/licenses/>.
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#ifndef RPIHARDWARE_H
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#define RPIHARDWARE_H
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#include <stdio.h>
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#include "types.h"
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#include "rpi-gpio.h"
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#include "debug.h"
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#define DMA_ENABLE (PERIPHERAL_BASE + 0x7FF0) // Global Enable bits for each DMA Channel
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#define DMA0_BASE (PERIPHERAL_BASE + 0x7000) // DMA Channel 0 Register Set
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#define DMA_CONBLK_AD 4 // DMA Channel 0..14 Control Block Address
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#define DMA_CS 0 // DMA Channel 0..14 Control & Status
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#define DMA_ACTIVE 1
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#define DMA_END 2
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#define DMA_DEST_DREQ 0x40
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#define DMA_SRC_INC 0x100
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#define DMA_PERMAP_5 0x50000
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#define ARM_GPIO_GPFSEL0 (RPI_GPIO_BASE + 0x00)
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#define ARM_GPIO_GPFSEL1 (RPI_GPIO_BASE + 0x04)
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#define ARM_GPIO_GPFSEL4 (RPI_GPIO_BASE + 0x10)
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#define ARM_GPIO_GPSET0 (RPI_GPIO_BASE + 0x1C)
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#define ARM_GPIO_GPCLR0 (RPI_GPIO_BASE + 0x28)
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#define ARM_GPIO_GPLEV0 (RPI_GPIO_BASE + 0x34)
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#define ARM_GPIO_GPEDS0 (RPI_GPIO_BASE + 0x40)
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#define ARM_GPIO_GPREN0 (RPI_GPIO_BASE + 0x4C)
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#define ARM_GPIO_GPFEN0 (RPI_GPIO_BASE + 0x58)
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#define ARM_GPIO_GPHEN0 (RPI_GPIO_BASE + 0x64)
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#define ARM_GPIO_GPLEN0 (RPI_GPIO_BASE + 0x70)
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#define ARM_GPIO_GPAREN0 (RPI_GPIO_BASE + 0x7C)
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#define ARM_GPIO_GPAFEN0 (RPI_GPIO_BASE + 0x88)
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#define ARM_GPIO_GPPUD (RPI_GPIO_BASE + 0x94)
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#define ARM_GPIO_GPPUDCLK0 (RPI_GPIO_BASE + 0x98)
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#define ARM_SYSTIMER_BASE (PERIPHERAL_BASE + 0x3000)
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#define ARM_SYSTIMER_CS (ARM_SYSTIMER_BASE + 0x00)
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#define ARM_SYSTIMER_CLO (ARM_SYSTIMER_BASE + 0x04)
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#define ARM_SYSTIMER_CHI (ARM_SYSTIMER_BASE + 0x08)
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#define ARM_SYSTIMER_C0 (ARM_SYSTIMER_BASE + 0x0C)
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#define ARM_SYSTIMER_C1 (ARM_SYSTIMER_BASE + 0x10)
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#define ARM_SYSTIMER_C2 (ARM_SYSTIMER_BASE + 0x14)
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#define ARM_SYSTIMER_C3 (ARM_SYSTIMER_BASE + 0x18)
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// External Mass Media Controller (SD Card)
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#define ARM_EMMC_BASE (PERIPHERAL_BASE + 0x300000)
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#define DEVICE_ID_SD_CARD 0
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#define DEVICE_ID_USB_HCD 3
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#define POWER_STATE_OFF (0 << 0)
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#define POWER_STATE_ON (1 << 0)
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#define POWER_STATE_WAIT (1 << 1)
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#define POWER_STATE_DEVICE_DOESNT_EXIST (1 << 1) // in response
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#define CLOCK_ID_EMMC 1
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#define CLOCK_ID_UART 2
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#define CLOCK_ID_CORE 4
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#define CM_BASE (PERIPHERAL_BASE + 0x101000)
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#define CM_PWMCTL (CM_BASE + 0xA0) // Clock Manager PWM Clock Control
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#define CM_PWMDIV (CM_BASE + 0xA4) // Clock Manager PWM Clock Divisor
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#define CM_PASSWORD 0x5A000000 // Clock Control Password "5A"
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#define CM_SRC_OSCILLATOR 0x01
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#define CM_ENAB 0x10 // Enable The Clock Generator
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#define PWM_BASE (PERIPHERAL_BASE + 0x20C000)
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#define PWM_CTL (PWM_BASE + 0x0)
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#define PWM_STATUS (PWM_BASE + 0x4)
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#define PWM_DMAC (PWM_BASE + 0x8)
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#define PWM_RNG1 (PWM_BASE + 0x10)
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#define PWM_FIF1 (PWM_BASE + 0x18) // PWM FIFO Input
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#define PWM_RNG2 (PWM_BASE + 0x20)
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#define PWM_ENAB 0x80000000 // PWM DMA Configuration DMA Enable
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#define PWM_PWEN1 0x1 // Channel 1 Enable
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#define PWM_MODE1 0x2 // Channel 1 Mode
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#define PWM_RPTL1 0x4 // Channel 1 Repeat Last Data
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#define PWM_SBIT1 0x8 // Channel 1 Silence Bit
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#define PWM_POLA1 0x10 // Channel 1 Polarity
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#define PWM_USEF1 0x20 // Channel 1 Use Fifo
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#define PWM_CLRF1 0x40 // Clear Fifo
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#define PWM_MSEN1 0x80 // Channel 1 M / S Enable
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#define PWM_PWEN2 0x100 // Channel 2 Enable
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#define PWM_MODE2 0x200 // Channel 2 Mode
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#define PWM_RPTL2 0x400 // Channel 2 Repeat Last Data
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#define PWM_SBIT2 0x800 // Channel 2 Silence Bit
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#define PWM_POLA2 0x1000 // Channel 2 Polarity
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#define PWM_USEF2 0x2000 // Channel 2 Use Fifo
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#define PWM_MSEN2 0x8000 // Channel 2 M / S Enable
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// PWM Status flags
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#define PWM_FULL1 0x1
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#define PWM_EMPT1 0x2
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//
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// Interrupt Controller
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//
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#define ARM_IC_BASE (PERIPHERAL_BASE + 0xB000)
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#define ARM_IC_IRQ_BASIC_PENDING (ARM_IC_BASE + 0x200)
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#define ARM_IC_IRQ_PENDING_1 (ARM_IC_BASE + 0x204)
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#define ARM_IC_IRQ_PENDING_2 (ARM_IC_BASE + 0x208)
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#define ARM_IC_FIQ_CONTROL (ARM_IC_BASE + 0x20C)
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#define ARM_IC_ENABLE_IRQS_1 (ARM_IC_BASE + 0x210)
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#define ARM_IC_ENABLE_IRQS_2 (ARM_IC_BASE + 0x214)
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#define ARM_IC_ENABLE_BASIC_IRQS (ARM_IC_BASE + 0x218)
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#define ARM_IC_DISABLE_IRQS_1 (ARM_IC_BASE + 0x21C)
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#define ARM_IC_DISABLE_IRQS_2 (ARM_IC_BASE + 0x220)
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#define ARM_IC_DISABLE_BASIC_IRQS (ARM_IC_BASE + 0x224)
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include "rpi-mailbox-interface.h"
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static inline u32 read32(unsigned int nAddress)
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{
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return *(u32 volatile *)nAddress;
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}
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static inline void write32(unsigned int nAddress, u32 nValue)
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{
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*(u32 volatile *)nAddress = nValue;
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}
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static inline void delay_us(u32 amount)
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{
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u32 count;
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for (count = 0; count < amount; ++count)
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{
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unsigned before;
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unsigned after;
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// We try to update every micro second and use as a rough timer to count micro seconds
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before = read32(ARM_SYSTIMER_CLO);
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do
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{
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after = read32(ARM_SYSTIMER_CLO);
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} while (after == before);
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}
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}
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static inline int get_clock_rate(int clk_id)
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{
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rpi_mailbox_property_t *buf;
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RPI_PropertyInit();
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RPI_PropertyAddTag(TAG_GET_CLOCK_RATE, clk_id);
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RPI_PropertyProcess();
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buf = RPI_PropertyGet(TAG_GET_CLOCK_RATE);
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if (buf)
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return buf->data.buffer_32[1];
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else
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return 0;
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}
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#ifdef __cplusplus
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}
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#endif
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//DMB - whenever a memory access requires ordering with regards to another memory access.
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//DSB - whenever a memory access needs to have completed before program execution progresses.
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//ISB - whenever instruction fetches need to explicitly take place after a certain point in the program, for example after memory map updates or after writing code to be executed. (In practice, this means "throw away any prefetched instructions at this point".)
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//DMB - It prevents reordering of data accesses instructions across itself. All data accesses by this processor / core before the DMB will be visible to all other masters within the specified shareability domain before any of the data accesses after it.
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// It also ensures that any explicit preceding data(or unified) cache maintenance operations have completed before any subsequent data accesses are executed.
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#if defined(RPI2) || defined(RPI3)
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#define DataSyncBarrier() asm volatile ("dsb" ::: "memory")
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#define DataMemBarrier() asm volatile ("dmb" ::: "memory")
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#define InstructionSyncBarrier() __asm volatile ("isb" ::: "memory")
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#define InstructionMemBarrier() __asm volatile ("isb" ::: "memory")
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#else
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#define DataSyncBarrier() asm volatile ("mcr p15, 0, %0, c7, c10, 4" : : "r" (0) : "memory")
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#define DataMemBarrier() asm volatile ("mcr p15, 0, %0, c7, c10, 5" : : "r" (0) : "memory")
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#define FlushPrefetchBuffer() __asm volatile ("mcr p15, 0, %0, c7, c5, 4" : : "r" (0) : "memory")
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#define InstructionSyncBarrier() FlushPrefetchBuffer()
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#define InstructionMemBarrier() FlushPrefetchBuffer()
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#endif
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#endif
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