75 lines
2.9 KiB
C
75 lines
2.9 KiB
C
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/*
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Part of the Raspberry-Pi Bare Metal Tutorials
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Copyright (c) 2013, Brian Sidebotham
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice,
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this list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef RPI_INTERRUPTS_H
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#define RPI_INTERRUPTS_H
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#include <stdint.h>
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#include "rpi-base.h"
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/** @brief See Section 7.5 of the BCM2836 ARM Peripherals documentation, the base
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address of the controller is actually xxxxB000, but there is a 0x200 offset
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to the first addressable register for the interrupt controller, so offset the
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base to the first register */
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#define RPI_INTERRUPT_CONTROLLER_BASE ( PERIPHERAL_BASE + 0xB200 )
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/** @brief Bits in the Enable_Basic_IRQs register to enable various interrupts.
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See the BCM2835 ARM Peripherals manual, section 7.5 */
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#define RPI_BASIC_ARM_TIMER_IRQ (1 << 0)
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#define RPI_BASIC_ARM_MAILBOX_IRQ (1 << 1)
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#define RPI_BASIC_ARM_DOORBELL_0_IRQ (1 << 2)
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#define RPI_BASIC_ARM_DOORBELL_1_IRQ (1 << 3)
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#define RPI_BASIC_GPU_0_HALTED_IRQ (1 << 4)
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#define RPI_BASIC_GPU_1_HALTED_IRQ (1 << 5)
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#define RPI_BASIC_ACCESS_ERROR_1_IRQ (1 << 6)
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#define RPI_BASIC_ACCESS_ERROR_0_IRQ (1 << 7)
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/** @brief The interrupt controller memory mapped register set */
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typedef struct {
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volatile uint32_t IRQ_basic_pending;
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volatile uint32_t IRQ_pending_1;
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volatile uint32_t IRQ_pending_2;
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volatile uint32_t FIQ_control;
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volatile uint32_t Enable_IRQs_1;
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volatile uint32_t Enable_IRQs_2;
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volatile uint32_t Enable_Basic_IRQs;
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volatile uint32_t Disable_IRQs_1;
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volatile uint32_t Disable_IRQs_2;
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volatile uint32_t Disable_Basic_IRQs;
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} rpi_irq_controller_t;
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extern rpi_irq_controller_t* RPI_GetIrqController( void );
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extern void reboot_now(void);
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#endif
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