72 lines
1.7 KiB
C
72 lines
1.7 KiB
C
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#ifndef DEFS_H
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#define DEFS_H
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#include "debug.h"
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// Indicates a Pi with the 40 pin GPIO connector
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// so that additional functionality (e.g. test pins) can be enabled
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#if defined(RPIZERO) || defined(RPIBPLUS) || defined(RPI2) || defined(RPI3)
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#define HAS_40PINS
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#endif
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// Pi 2/3 Multicore options
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#if defined(RPI2) || defined(RPI3)
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// Indicate the platform has multiple cores
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#define HAS_MULTICORE
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#define USE_GPU
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#define USE_HW_MAILBOX
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// Indicates we want to make active use of multiple cores
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#define USE_MULTICORE
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// Needs to match kernel_old setting in config.txt
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//#define KERNEL_OLD
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// Include instruction histogram in multi core 65tube
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//#define HISTOGRAM
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#else
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#define USE_GPU
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#define USE_HW_MAILBOX
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#endif
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#include "rpi-base.h"
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#ifdef USE_HW_MAILBOX
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#define MBOX0_READ (PERIPHERAL_BASE + 0x00B880)
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#define MBOX0_STATUS (PERIPHERAL_BASE + 0x00B898)
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#define MBOX0_CONFIG (PERIPHERAL_BASE + 0x00B89C)
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#define MBOX0_EMPTY (0x40000000)
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#define MBOX0_DATAIRQEN (0x00000001)
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#endif
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#ifdef __ASSEMBLER__
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#define GPFSEL0 (PERIPHERAL_BASE + 0x200000) // controls GPIOs 0..9
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#define GPFSEL1 (PERIPHERAL_BASE + 0x200004) // controls GPIOs 10..19
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#define GPFSEL2 (PERIPHERAL_BASE + 0x200008) // controls GPIOs 20..29
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#define GPSET0 (PERIPHERAL_BASE + 0x20001C)
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#define GPCLR0 (PERIPHERAL_BASE + 0x200028)
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#define GPLEV0 (PERIPHERAL_BASE + 0x200034)
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#define GPEDS0 (PERIPHERAL_BASE + 0x200040)
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#define FIQCTRL (PERIPHERAL_BASE + 0x00B20C)
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#endif // __ASSEMBLER__
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#ifdef HAS_40PINS
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#define TEST_PIN (21)
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#define TEST_MASK (1 << TEST_PIN)
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#define TEST2_PIN (20)
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#define TEST2_MASK (1 << TEST2_PIN)
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#define TEST3_PIN (16)
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#define TEST3_MASK (1 << TEST3_PIN)
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#endif
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#endif
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