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Some code restructing and removed writeshiftregister use.

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Moved the branching to Update.
writeShiftRegister renamed.
Fixed typo in main drive read.
Reorganised SetInput call try to trigger conditionals.
This commit is contained in:
Alexander Martinelle 2019-09-04 22:06:21 +02:00
parent 3978ef2165
commit 2d538e4975
2 changed files with 51 additions and 71 deletions
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119
src/Drive.cpp
View file

@ -473,7 +473,22 @@ bool Drive::Update()
if (writing) if (writing)
DriveLoopWrite(); DriveLoopWrite();
else else
DriveLoopRead(); {
if (fluxReversalCyclesLeft > 16 && cyclesLeftForBit > 16)
{
DriveLoopReadNoFluxNoCycles();
}
else if (fluxReversalCyclesLeft > 16)
{
DriveLoopReadNoFlux();
}
else if (cyclesLeftForBit > 16)
{
DriveLoopReadNoCycles();
}
else
DriveLoopRead();
}
#else #else
for (int cycles = 0; cycles < 16; ++cycles) for (int cycles = 0; cycles < 16; ++cycles)
{ {
@ -593,28 +608,24 @@ void Drive::DriveLoopReadNoFluxNoCycles()
if ((UF4Counter & 0x3) == 2) if ((UF4Counter & 0x3) == 2)
{ {
readShiftRegister <<= 1; readShiftRegister <<= 1;
readShiftRegister |= (UF4Counter == 2); // Emulate UE5A and only shift in a 1 when pins 6 (output C) and 7 (output D) (bits 2 and 3 of UF4Counter are 0. ie the first count of the bit cell) readShiftRegister |= (UF4Counter == 2);
writeShiftRegister <<= 1; //writeShiftRegister <<= 1;
// Note: SYNC can only trigger during reading as R/!W line is one of UC2's inputs.
if (((readShiftRegister & 0x3ff) == 0x3ff)) // if the last 10 bits are 1s then SYNC bool resetTime = ((readShiftRegister & 0x3ff) == 0x3ff);
{ m_pVIA->GetPortB()->SetInput(0x80, !resetTime);
if (resetTime) // if the last 10 bits are 1s then SYNC
UE3Counter = 0; // Phase lock on to byte boundary UE3Counter = 0; // Phase lock on to byte boundary
m_pVIA->GetPortB()->SetInput(0x80, false); // PB7 active low SYNC
}
else else
{
m_pVIA->GetPortB()->SetInput(0x80, true); // SYNC not asserted if not following the SYNC bits
UE3Counter++; UE3Counter++;
}
} }
// UC5B (NOR used to invert UF4's output B serial clock) output high when UF4 counts 0,1,4,5,8,9,12 and 13 // UC5B (NOR used to invert UF4's output B serial clock) output high when UF4 counts 0,1,4,5,8,9,12 and 13
else if (((UF4Counter & 2) == 0) && (UE3Counter == 8)) // Phase locked on to byte boundary else if (((UF4Counter & 2) == 0) && (UE3Counter == 8)) // Phase locked on to byte boundary
{ {
UE3Counter = 0; UE3Counter = 0;
SO = (m_pVIA->GetFCR() & m6522::FCR_CA2_OUTPUT_MODE0) != 0; // bit 2 of the FCR indicates "Byte Ready Active" turned on or not. SO = (m_pVIA->GetFCR() & m6522::FCR_CA2_OUTPUT_MODE0) != 0; // bit 2 of the FCR indicates "Byte Ready Active" turned on or not.
writeShiftRegister = (u8)(readShiftRegister & 0xff); // writeShiftRegister = readShiftRegister;
m_pVIA->GetPortA()->SetInput(writeShiftRegister); m_pVIA->GetPortA()->SetInput(readShiftRegister & 0xff);
} }
}; };
} }
@ -667,28 +678,24 @@ void Drive::DriveLoopReadNoFlux()
if ((UF4Counter & 0x3) == 2) if ((UF4Counter & 0x3) == 2)
{ {
readShiftRegister <<= 1; readShiftRegister <<= 1;
readShiftRegister |= (UF4Counter == 2); // Emulate UE5A and only shift in a 1 when pins 6 (output C) and 7 (output D) (bits 2 and 3 of UF4Counter are 0. ie the first count of the bit cell) readShiftRegister |= (UF4Counter == 2);
writeShiftRegister <<= 1; //writeShiftRegister <<= 1;
// Note: SYNC can only trigger during reading as R/!W line is one of UC2's inputs.
if (((readShiftRegister & 0x3ff) == 0x3ff)) // if the last 10 bits are 1s then SYNC bool resetTime = ((readShiftRegister & 0x3ff) == 0x3ff);
{ m_pVIA->GetPortB()->SetInput(0x80, !resetTime);
if (resetTime) // if the last 10 bits are 1s then SYNC
UE3Counter = 0; // Phase lock on to byte boundary UE3Counter = 0; // Phase lock on to byte boundary
m_pVIA->GetPortB()->SetInput(0x80, false); // PB7 active low SYNC
}
else else
{
m_pVIA->GetPortB()->SetInput(0x80, true); // SYNC not asserted if not following the SYNC bits
UE3Counter++; UE3Counter++;
}
} }
// UC5B (NOR used to invert UF4's output B serial clock) output high when UF4 counts 0,1,4,5,8,9,12 and 13 // UC5B (NOR used to invert UF4's output B serial clock) output high when UF4 counts 0,1,4,5,8,9,12 and 13
else if (((UF4Counter & 2) == 0) && (UE3Counter == 8)) // Phase locked on to byte boundary else if (((UF4Counter & 2) == 0) && (UE3Counter == 8)) // Phase locked on to byte boundary
{ {
UE3Counter = 0; UE3Counter = 0;
SO = (m_pVIA->GetFCR() & m6522::FCR_CA2_OUTPUT_MODE0) != 0; // bit 2 of the FCR indicates "Byte Ready Active" turned on or not. SO = (m_pVIA->GetFCR() & m6522::FCR_CA2_OUTPUT_MODE0) != 0; // bit 2 of the FCR indicates "Byte Ready Active" turned on or not.
writeShiftRegister = (u8)(readShiftRegister & 0xff); // writeShiftRegister = readShiftRegister;
m_pVIA->GetPortA()->SetInput(writeShiftRegister); m_pVIA->GetPortA()->SetInput(readShiftRegister & 0xff);
} }
} }
}; };
@ -724,53 +731,30 @@ void Drive::DriveLoopReadNoCycles()
if ((UF4Counter & 0x3) == 2) if ((UF4Counter & 0x3) == 2)
{ {
readShiftRegister <<= 1; readShiftRegister <<= 1;
readShiftRegister |= (UF4Counter == 2); // Emulate UE5A and only shift in a 1 when pins 6 (output C) and 7 (output D) (bits 2 and 3 of UF4Counter are 0. ie the first count of the bit cell) readShiftRegister |= (UF4Counter == 2);
writeShiftRegister <<= 1; //writeShiftRegister <<= 1;
// Note: SYNC can only trigger during reading as R/!W line is one of UC2's inputs.
if (((readShiftRegister & 0x3ff) == 0x3ff)) // if the last 10 bits are 1s then SYNC bool resetTime = ((readShiftRegister & 0x3ff) == 0x3ff);
{ m_pVIA->GetPortB()->SetInput(0x80, !resetTime);
if (resetTime) // if the last 10 bits are 1s then SYNC
UE3Counter = 0; // Phase lock on to byte boundary UE3Counter = 0; // Phase lock on to byte boundary
m_pVIA->GetPortB()->SetInput(0x80, false); // PB7 active low SYNC
}
else else
{
m_pVIA->GetPortB()->SetInput(0x80, true); // SYNC not asserted if not following the SYNC bits
UE3Counter++; UE3Counter++;
}
} }
// UC5B (NOR used to invert UF4's output B serial clock) output high when UF4 counts 0,1,4,5,8,9,12 and 13 // UC5B (NOR used to invert UF4's output B serial clock) output high when UF4 counts 0,1,4,5,8,9,12 and 13
else if (((UF4Counter & 2) == 0) && (UE3Counter == 8)) // Phase locked on to byte boundary else if (((UF4Counter & 2) == 0) && (UE3Counter == 8)) // Phase locked on to byte boundary
{ {
UE3Counter = 0; UE3Counter = 0;
SO = (m_pVIA->GetFCR() & m6522::FCR_CA2_OUTPUT_MODE0) != 0; // bit 2 of the FCR indicates "Byte Ready Active" turned on or not. SO = (m_pVIA->GetFCR() & m6522::FCR_CA2_OUTPUT_MODE0) != 0; // bit 2 of the FCR indicates "Byte Ready Active" turned on or not.
writeShiftRegister = (u8)(readShiftRegister & 0xff); // writeShiftRegister = readShiftRegister;
m_pVIA->GetPortA()->SetInput(writeShiftRegister); m_pVIA->GetPortA()->SetInput(readShiftRegister & 0xff);
} }
} }
}; };
} }
void Drive::DriveLoopRead() void Drive::DriveLoopRead()
{ {
if (fluxReversalCyclesLeft > 16 && cyclesLeftForBit > 16)
{
DriveLoopReadNoFluxNoCycles();
return;
}
if (fluxReversalCyclesLeft > 16)
{
DriveLoopReadNoFlux();
return;
}
if (cyclesLeftForBit > 16)
{
DriveLoopReadNoCycles();
return;
}
unsigned int minCycles; unsigned int minCycles;
unsigned int cycles = 16; unsigned int cycles = 16;
@ -818,32 +802,27 @@ void Drive::DriveLoopRead()
++UF4Counter &= 0xf; // Clock and clamp UF4. ++UF4Counter &= 0xf; // Clock and clamp UF4.
// The UD2 read shift register is clocked by serial clock (the rising edge of encoder/decoder's UF4 B output (serial clock)) // The UD2 read shift register is clocked by serial clock (the rising edge of encoder/decoder's UF4 B output (serial clock))
// - ie on counts 2, 6, 10 and 14 (2 is the only count that outputs a 1 into readShiftRegister as the MSB bits of the count NORed together for other values are 0) // - ie on counts 2, 6, 10 and 14 (2 is the only count that outputs a 1 into readShiftRegister as the MSB bits of the count NORed together for other values are 0)
//if ((UF4Counter & 0x3) == 2) if ((UF4Counter & 0x3) == 2)
if (UF4Counter == 2 || UF4Counter == 6) //You'd think the bit operation should be faster...
{ {
readShiftRegister <<= 1; readShiftRegister <<= 1;
readShiftRegister |= (UF4Counter == 2); // Emulate UE5A and only shift in a 1 when pins 6 (output C) and 7 (output D) (bits 2 and 3 of UF4Counter are 0. ie the first count of the bit cell) readShiftRegister |= (UF4Counter == 2);
writeShiftRegister <<= 1; //writeShiftRegister <<= 1;
// Note: SYNC can only trigger during reading as R/!W line is one of UC2's inputs.
if (((readShiftRegister & 0x3ff) == 0x3ff)) // if the last 10 bits are 1s then SYNC bool resetTime = ((readShiftRegister & 0x3ff) == 0x3ff);
{ m_pVIA->GetPortB()->SetInput(0x80, !resetTime);
if (resetTime) // if the last 10 bits are 1s then SYNC
UE3Counter = 0; // Phase lock on to byte boundary UE3Counter = 0; // Phase lock on to byte boundary
m_pVIA->GetPortB()->SetInput(0x80, false); // PB7 active low SYNC
}
else else
{
m_pVIA->GetPortB()->SetInput(0x80, true); // SYNC not asserted if not following the SYNC bits
UE3Counter++; UE3Counter++;
}
} }
// UC5B (NOR used to invert UF4's output B serial clock) output high when UF4 counts 0,1,4,5,8,9,12 and 13 // UC5B (NOR used to invert UF4's output B serial clock) output high when UF4 counts 0,1,4,5,8,9,12 and 13
else if (((UF4Counter & 2) == 0) && (UE3Counter == 8)) // Phase locked on to byte boundary else if (((UF4Counter & 2) == 0) && (UE3Counter == 8)) // Phase locked on to byte boundary
{ {
UE3Counter = 0; UE3Counter = 0;
SO = (m_pVIA->GetFCR() & m6522::FCR_CA2_OUTPUT_MODE0) != 0; // bit 2 of the FCR indicates "Byte Ready Active" turned on or not. SO = (m_pVIA->GetFCR() & m6522::FCR_CA2_OUTPUT_MODE0) != 0; // bit 2 of the FCR indicates "Byte Ready Active" turned on or not.
writeShiftRegister = (u8)(readShiftRegister & 0xff); // writeShiftRegister = readShiftRegister;
m_pVIA->GetPortA()->SetInput(writeShiftRegister); m_pVIA->GetPortA()->SetInput(readShiftRegister & 0xff);
} }
} }
}; };

3
src/Drive.h
View file

@ -166,8 +166,10 @@ private:
unsigned int cyclesLeftForBit; unsigned int cyclesLeftForBit;
unsigned int fluxReversalCyclesLeft; unsigned int fluxReversalCyclesLeft;
unsigned int UE7Counter; unsigned int UE7Counter;
u32 writeShiftRegister;
#else #else
int UE7Counter; int UE7Counter;
u8 writeShiftRegister;
#endif #endif
float cyclesForBit; float cyclesForBit;
u32 readShiftRegister; u32 readShiftRegister;
@ -183,6 +185,5 @@ private:
float cyclesPerBit; float cyclesPerBit;
bool motor; bool motor;
bool LED; bool LED;
u8 writeShiftRegister;
}; };
#endif #endif