Some code restructing and removed writeshiftregister use.
Moved the branching to Update. writeShiftRegister renamed. Fixed typo in main drive read. Reorganised SetInput call try to trigger conditionals.
This commit is contained in:
Alexander Martinelle
parent
3978ef2165
commit
2d538e4975
2 changed files with 51 additions and 71 deletions
117
src/Drive.cpp
117
src/Drive.cpp
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@ -472,8 +472,23 @@ bool Drive::Update()
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#if defined(EXPERIMENTALZERO)
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if (writing)
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DriveLoopWrite();
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else
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{
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if (fluxReversalCyclesLeft > 16 && cyclesLeftForBit > 16)
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{
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DriveLoopReadNoFluxNoCycles();
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}
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else if (fluxReversalCyclesLeft > 16)
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{
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DriveLoopReadNoFlux();
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}
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else if (cyclesLeftForBit > 16)
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{
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DriveLoopReadNoCycles();
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}
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else
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DriveLoopRead();
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}
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#else
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for (int cycles = 0; cycles < 16; ++cycles)
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{
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@ -593,28 +608,24 @@ void Drive::DriveLoopReadNoFluxNoCycles()
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if ((UF4Counter & 0x3) == 2)
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{
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readShiftRegister <<= 1;
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readShiftRegister |= (UF4Counter == 2); // Emulate UE5A and only shift in a 1 when pins 6 (output C) and 7 (output D) (bits 2 and 3 of UF4Counter are 0. ie the first count of the bit cell)
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readShiftRegister |= (UF4Counter == 2);
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writeShiftRegister <<= 1;
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// Note: SYNC can only trigger during reading as R/!W line is one of UC2's inputs.
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if (((readShiftRegister & 0x3ff) == 0x3ff)) // if the last 10 bits are 1s then SYNC
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{
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//writeShiftRegister <<= 1;
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bool resetTime = ((readShiftRegister & 0x3ff) == 0x3ff);
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m_pVIA->GetPortB()->SetInput(0x80, !resetTime);
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if (resetTime) // if the last 10 bits are 1s then SYNC
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UE3Counter = 0; // Phase lock on to byte boundary
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m_pVIA->GetPortB()->SetInput(0x80, false); // PB7 active low SYNC
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}
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else
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{
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m_pVIA->GetPortB()->SetInput(0x80, true); // SYNC not asserted if not following the SYNC bits
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UE3Counter++;
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}
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}
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// UC5B (NOR used to invert UF4's output B serial clock) output high when UF4 counts 0,1,4,5,8,9,12 and 13
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else if (((UF4Counter & 2) == 0) && (UE3Counter == 8)) // Phase locked on to byte boundary
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{
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UE3Counter = 0;
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SO = (m_pVIA->GetFCR() & m6522::FCR_CA2_OUTPUT_MODE0) != 0; // bit 2 of the FCR indicates "Byte Ready Active" turned on or not.
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writeShiftRegister = (u8)(readShiftRegister & 0xff);
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m_pVIA->GetPortA()->SetInput(writeShiftRegister);
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// writeShiftRegister = readShiftRegister;
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m_pVIA->GetPortA()->SetInput(readShiftRegister & 0xff);
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}
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};
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}
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@ -667,28 +678,24 @@ void Drive::DriveLoopReadNoFlux()
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if ((UF4Counter & 0x3) == 2)
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{
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readShiftRegister <<= 1;
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readShiftRegister |= (UF4Counter == 2); // Emulate UE5A and only shift in a 1 when pins 6 (output C) and 7 (output D) (bits 2 and 3 of UF4Counter are 0. ie the first count of the bit cell)
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readShiftRegister |= (UF4Counter == 2);
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writeShiftRegister <<= 1;
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// Note: SYNC can only trigger during reading as R/!W line is one of UC2's inputs.
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if (((readShiftRegister & 0x3ff) == 0x3ff)) // if the last 10 bits are 1s then SYNC
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{
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//writeShiftRegister <<= 1;
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bool resetTime = ((readShiftRegister & 0x3ff) == 0x3ff);
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m_pVIA->GetPortB()->SetInput(0x80, !resetTime);
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if (resetTime) // if the last 10 bits are 1s then SYNC
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UE3Counter = 0; // Phase lock on to byte boundary
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m_pVIA->GetPortB()->SetInput(0x80, false); // PB7 active low SYNC
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}
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else
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{
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m_pVIA->GetPortB()->SetInput(0x80, true); // SYNC not asserted if not following the SYNC bits
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UE3Counter++;
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}
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}
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// UC5B (NOR used to invert UF4's output B serial clock) output high when UF4 counts 0,1,4,5,8,9,12 and 13
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else if (((UF4Counter & 2) == 0) && (UE3Counter == 8)) // Phase locked on to byte boundary
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{
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UE3Counter = 0;
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SO = (m_pVIA->GetFCR() & m6522::FCR_CA2_OUTPUT_MODE0) != 0; // bit 2 of the FCR indicates "Byte Ready Active" turned on or not.
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writeShiftRegister = (u8)(readShiftRegister & 0xff);
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m_pVIA->GetPortA()->SetInput(writeShiftRegister);
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// writeShiftRegister = readShiftRegister;
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m_pVIA->GetPortA()->SetInput(readShiftRegister & 0xff);
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}
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}
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};
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@ -724,53 +731,30 @@ void Drive::DriveLoopReadNoCycles()
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if ((UF4Counter & 0x3) == 2)
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{
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readShiftRegister <<= 1;
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readShiftRegister |= (UF4Counter == 2); // Emulate UE5A and only shift in a 1 when pins 6 (output C) and 7 (output D) (bits 2 and 3 of UF4Counter are 0. ie the first count of the bit cell)
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readShiftRegister |= (UF4Counter == 2);
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writeShiftRegister <<= 1;
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// Note: SYNC can only trigger during reading as R/!W line is one of UC2's inputs.
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if (((readShiftRegister & 0x3ff) == 0x3ff)) // if the last 10 bits are 1s then SYNC
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{
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//writeShiftRegister <<= 1;
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bool resetTime = ((readShiftRegister & 0x3ff) == 0x3ff);
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m_pVIA->GetPortB()->SetInput(0x80, !resetTime);
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if (resetTime) // if the last 10 bits are 1s then SYNC
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UE3Counter = 0; // Phase lock on to byte boundary
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m_pVIA->GetPortB()->SetInput(0x80, false); // PB7 active low SYNC
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}
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else
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{
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m_pVIA->GetPortB()->SetInput(0x80, true); // SYNC not asserted if not following the SYNC bits
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UE3Counter++;
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}
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}
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// UC5B (NOR used to invert UF4's output B serial clock) output high when UF4 counts 0,1,4,5,8,9,12 and 13
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else if (((UF4Counter & 2) == 0) && (UE3Counter == 8)) // Phase locked on to byte boundary
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{
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UE3Counter = 0;
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SO = (m_pVIA->GetFCR() & m6522::FCR_CA2_OUTPUT_MODE0) != 0; // bit 2 of the FCR indicates "Byte Ready Active" turned on or not.
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writeShiftRegister = (u8)(readShiftRegister & 0xff);
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m_pVIA->GetPortA()->SetInput(writeShiftRegister);
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// writeShiftRegister = readShiftRegister;
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m_pVIA->GetPortA()->SetInput(readShiftRegister & 0xff);
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}
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}
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};
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}
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void Drive::DriveLoopRead()
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{
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if (fluxReversalCyclesLeft > 16 && cyclesLeftForBit > 16)
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{
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DriveLoopReadNoFluxNoCycles();
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return;
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}
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if (fluxReversalCyclesLeft > 16)
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{
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DriveLoopReadNoFlux();
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return;
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}
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if (cyclesLeftForBit > 16)
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{
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DriveLoopReadNoCycles();
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return;
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}
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unsigned int minCycles;
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unsigned int cycles = 16;
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@ -818,32 +802,27 @@ void Drive::DriveLoopRead()
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++UF4Counter &= 0xf; // Clock and clamp UF4.
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// The UD2 read shift register is clocked by serial clock (the rising edge of encoder/decoder's UF4 B output (serial clock))
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// - ie on counts 2, 6, 10 and 14 (2 is the only count that outputs a 1 into readShiftRegister as the MSB bits of the count NORed together for other values are 0)
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//if ((UF4Counter & 0x3) == 2)
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if (UF4Counter == 2 || UF4Counter == 6) //You'd think the bit operation should be faster...
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if ((UF4Counter & 0x3) == 2)
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{
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readShiftRegister <<= 1;
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readShiftRegister |= (UF4Counter == 2); // Emulate UE5A and only shift in a 1 when pins 6 (output C) and 7 (output D) (bits 2 and 3 of UF4Counter are 0. ie the first count of the bit cell)
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readShiftRegister |= (UF4Counter == 2);
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writeShiftRegister <<= 1;
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// Note: SYNC can only trigger during reading as R/!W line is one of UC2's inputs.
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if (((readShiftRegister & 0x3ff) == 0x3ff)) // if the last 10 bits are 1s then SYNC
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{
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//writeShiftRegister <<= 1;
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bool resetTime = ((readShiftRegister & 0x3ff) == 0x3ff);
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m_pVIA->GetPortB()->SetInput(0x80, !resetTime);
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if (resetTime) // if the last 10 bits are 1s then SYNC
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UE3Counter = 0; // Phase lock on to byte boundary
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m_pVIA->GetPortB()->SetInput(0x80, false); // PB7 active low SYNC
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}
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else
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{
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m_pVIA->GetPortB()->SetInput(0x80, true); // SYNC not asserted if not following the SYNC bits
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UE3Counter++;
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}
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}
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// UC5B (NOR used to invert UF4's output B serial clock) output high when UF4 counts 0,1,4,5,8,9,12 and 13
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else if (((UF4Counter & 2) == 0) && (UE3Counter == 8)) // Phase locked on to byte boundary
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{
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UE3Counter = 0;
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SO = (m_pVIA->GetFCR() & m6522::FCR_CA2_OUTPUT_MODE0) != 0; // bit 2 of the FCR indicates "Byte Ready Active" turned on or not.
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writeShiftRegister = (u8)(readShiftRegister & 0xff);
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m_pVIA->GetPortA()->SetInput(writeShiftRegister);
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// writeShiftRegister = readShiftRegister;
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m_pVIA->GetPortA()->SetInput(readShiftRegister & 0xff);
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}
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}
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};
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@ -166,8 +166,10 @@ private:
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unsigned int cyclesLeftForBit;
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unsigned int fluxReversalCyclesLeft;
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unsigned int UE7Counter;
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u32 writeShiftRegister;
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#else
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int UE7Counter;
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u8 writeShiftRegister;
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#endif
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float cyclesForBit;
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u32 readShiftRegister;
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@ -183,6 +185,5 @@ private:
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float cyclesPerBit;
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bool motor;
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bool LED;
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u8 writeShiftRegister;
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};
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#endif
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