1541 Drive speed improvements
Specialized drive read loops for the most common cases, triggers a vast speed improvement in some scenarios. Improved saving speed. Removed some more code that's not really required right now.
This commit is contained in:
Alexander Martinelle
parent
bddc9a7d29
commit
3978ef2165
5 changed files with 259 additions and 55 deletions
254
src/Drive.cpp
254
src/Drive.cpp
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@ -358,6 +358,7 @@ void Drive::Reset()
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#if defined(EXPERIMENTALZERO)
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LED = false;
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cyclesForBit = 0;
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UE7Counter = 16;
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#endif
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headTrackPos = 18*2; // Start with the head over track 19 (Very later Vorpal ie Cakifornia Games) need to have had the last head movement -ve
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CLOCK_SEL_AB = 3; // Track 18 will use speed zone 3 (encoder/decoder (ie UE7Counter) clocked at 1.2307Mhz)
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@ -568,20 +569,71 @@ bool Drive::Update()
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#define min(a,b) (((a) < (b)) ? (a) : (b))
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#define max(a,b) (((a) > (b)) ? (a) : (b))
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void Drive::DriveLoopRead()
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void Drive::DriveLoopReadNoFluxNoCycles()
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{
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unsigned int cycles = 16;
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fluxReversalCyclesLeft -= 16;
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cyclesLeftForBit -= 16;
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while (true)
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{
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if (cycles < UE7Counter)
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{
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UE7Counter -= cycles;
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cycles = 0;
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return;
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}
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cycles -= UE7Counter;
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UE7Counter = 16 - CLOCK_SEL_AB; // A and B inputs of UE7 come from the VIA's CLOCK SEL A/B outputs (ie PB5/6) ie preload the encoder/decoder clock for the current density settings.
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// The decoder consists of UF4 and UE5A. The ecoder has two outputs, Pin 1 of UE5A is the serial data output and pin 2 of UF4 (output B) is the serial clock output.
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++UF4Counter &= 0xf; // Clock and clamp UF4.
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// The UD2 read shift register is clocked by serial clock (the rising edge of encoder/decoder's UF4 B output (serial clock))
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// - ie on counts 2, 6, 10 and 14 (2 is the only count that outputs a 1 into readShiftRegister as the MSB bits of the count NORed together for other values are 0)
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if ((UF4Counter & 0x3) == 2)
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{
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readShiftRegister <<= 1;
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readShiftRegister |= (UF4Counter == 2); // Emulate UE5A and only shift in a 1 when pins 6 (output C) and 7 (output D) (bits 2 and 3 of UF4Counter are 0. ie the first count of the bit cell)
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writeShiftRegister <<= 1;
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// Note: SYNC can only trigger during reading as R/!W line is one of UC2's inputs.
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if (((readShiftRegister & 0x3ff) == 0x3ff)) // if the last 10 bits are 1s then SYNC
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{
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UE3Counter = 0; // Phase lock on to byte boundary
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m_pVIA->GetPortB()->SetInput(0x80, false); // PB7 active low SYNC
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}
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else
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{
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m_pVIA->GetPortB()->SetInput(0x80, true); // SYNC not asserted if not following the SYNC bits
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UE3Counter++;
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}
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}
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// UC5B (NOR used to invert UF4's output B serial clock) output high when UF4 counts 0,1,4,5,8,9,12 and 13
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else if (((UF4Counter & 2) == 0) && (UE3Counter == 8)) // Phase locked on to byte boundary
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{
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UE3Counter = 0;
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SO = (m_pVIA->GetFCR() & m6522::FCR_CA2_OUTPUT_MODE0) != 0; // bit 2 of the FCR indicates "Byte Ready Active" turned on or not.
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writeShiftRegister = (u8)(readShiftRegister & 0xff);
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m_pVIA->GetPortA()->SetInput(writeShiftRegister);
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}
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};
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}
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void Drive::DriveLoopReadNoFlux()
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{
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unsigned int minCycles;
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unsigned int cycles = 0;
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unsigned int cycles = 16;
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fluxReversalCyclesLeft -= 16;
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while (true)
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{
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minCycles = min(min(cyclesLeftForBit, fluxReversalCyclesLeft), 16 - max(UE7Counter, cycles));
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minCycles = min(min(cyclesLeftForBit, cycles), UE7Counter);
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cyclesLeftForBit -= minCycles;
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fluxReversalCyclesLeft -= minCycles;
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cycles += minCycles;
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UE7Counter += minCycles;
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cycles -= minCycles;
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UE7Counter -= minCycles;
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if (cycles == 16)
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if (cycles == 0)
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return;
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if (cyclesLeftForBit == 0)
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@ -605,14 +657,9 @@ void Drive::DriveLoopRead()
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}
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}
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if (fluxReversalCyclesLeft == 0)//Not entirely right, a flux reversal will be skipped if a bit read was going to happen
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if (UE7Counter == 0x0) // The count carry (bit 4) clocks UF4.
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{
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ResetEncoderDecoder(2 * 16, /*25 * 16*/23 * 16); // Trigger a random noise generated zero crossing and start seeing more anywhere between 2us and 25us after this one.
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}
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if (UE7Counter == 0x10) // The count carry (bit 4) clocks UF4.
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{
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UE7Counter = CLOCK_SEL_AB; // A and B inputs of UE7 come from the VIA's CLOCK SEL A/B outputs (ie PB5/6) ie preload the encoder/decoder clock for the current density settings.
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UE7Counter = 16 - CLOCK_SEL_AB; // A and B inputs of UE7 come from the VIA's CLOCK SEL A/B outputs (ie PB5/6) ie preload the encoder/decoder clock for the current density settings.
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// The decoder consists of UF4 and UE5A. The ecoder has two outputs, Pin 1 of UE5A is the serial data output and pin 2 of UF4 (output B) is the serial clock output.
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++UF4Counter &= 0xf; // Clock and clamp UF4.
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// The UD2 read shift register is clocked by serial clock (the rising edge of encoder/decoder's UF4 B output (serial clock))
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@ -644,21 +691,179 @@ void Drive::DriveLoopRead()
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m_pVIA->GetPortA()->SetInput(writeShiftRegister);
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}
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}
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};
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}
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void Drive::DriveLoopReadNoCycles()
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{
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unsigned int minCycles;
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unsigned int cycles = 16;
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cyclesLeftForBit -= 16;
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while (true)
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{
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minCycles = min(cycles, min(UE7Counter, fluxReversalCyclesLeft));
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fluxReversalCyclesLeft -= minCycles;
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cycles -= minCycles;
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UE7Counter -= minCycles;
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if (cycles == 0)
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return;
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if (fluxReversalCyclesLeft == 0)//Not entirely right, a flux reversal will be skipped if a bit read was going to happen
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{
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ResetEncoderDecoder(2 * 16, /*25 * 16*/23 * 16); // Trigger a random noise generated zero crossing and start seeing more anywhere between 2us and 25us after this one.
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}
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if (UE7Counter == 0x0) // The count carry (bit 4) clocks UF4.
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{
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UE7Counter = 16 - CLOCK_SEL_AB; // A and B inputs of UE7 come from the VIA's CLOCK SEL A/B outputs (ie PB5/6) ie preload the encoder/decoder clock for the current density settings.
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// The decoder consists of UF4 and UE5A. The ecoder has two outputs, Pin 1 of UE5A is the serial data output and pin 2 of UF4 (output B) is the serial clock output.
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++UF4Counter &= 0xf; // Clock and clamp UF4.
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// The UD2 read shift register is clocked by serial clock (the rising edge of encoder/decoder's UF4 B output (serial clock))
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// - ie on counts 2, 6, 10 and 14 (2 is the only count that outputs a 1 into readShiftRegister as the MSB bits of the count NORed together for other values are 0)
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if ((UF4Counter & 0x3) == 2)
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{
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readShiftRegister <<= 1;
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readShiftRegister |= (UF4Counter == 2); // Emulate UE5A and only shift in a 1 when pins 6 (output C) and 7 (output D) (bits 2 and 3 of UF4Counter are 0. ie the first count of the bit cell)
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writeShiftRegister <<= 1;
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// Note: SYNC can only trigger during reading as R/!W line is one of UC2's inputs.
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if (((readShiftRegister & 0x3ff) == 0x3ff)) // if the last 10 bits are 1s then SYNC
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{
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UE3Counter = 0; // Phase lock on to byte boundary
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m_pVIA->GetPortB()->SetInput(0x80, false); // PB7 active low SYNC
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}
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else
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{
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m_pVIA->GetPortB()->SetInput(0x80, true); // SYNC not asserted if not following the SYNC bits
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UE3Counter++;
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}
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}
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// UC5B (NOR used to invert UF4's output B serial clock) output high when UF4 counts 0,1,4,5,8,9,12 and 13
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else if (((UF4Counter & 2) == 0) && (UE3Counter == 8)) // Phase locked on to byte boundary
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{
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UE3Counter = 0;
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SO = (m_pVIA->GetFCR() & m6522::FCR_CA2_OUTPUT_MODE0) != 0; // bit 2 of the FCR indicates "Byte Ready Active" turned on or not.
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writeShiftRegister = (u8)(readShiftRegister & 0xff);
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m_pVIA->GetPortA()->SetInput(writeShiftRegister);
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}
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}
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};
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}
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void Drive::DriveLoopRead()
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{
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if (fluxReversalCyclesLeft > 16 && cyclesLeftForBit > 16)
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{
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DriveLoopReadNoFluxNoCycles();
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return;
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}
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if (fluxReversalCyclesLeft > 16)
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{
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DriveLoopReadNoFlux();
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return;
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}
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if (cyclesLeftForBit > 16)
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{
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DriveLoopReadNoCycles();
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return;
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}
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unsigned int minCycles;
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unsigned int cycles = 16;
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while (true)
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{
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minCycles = min(min(cyclesLeftForBit, cycles), min(UE7Counter, fluxReversalCyclesLeft));
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cyclesLeftForBit -= minCycles;
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fluxReversalCyclesLeft -= minCycles;
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cycles -= minCycles;
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UE7Counter -= minCycles;
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if (cycles == 0)
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return;
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if (cyclesLeftForBit == 0)
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{
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//which is faster? single loop ceil check or the 3 lines below?
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float fn = 2.0f * cyclesPerBit - cyclesForBit;
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cyclesLeftForBit = (int)fn;
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cyclesForBit = cyclesPerBit;
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if (fn != (float)cyclesLeftForBit) {
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++cyclesLeftForBit;
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++cyclesForBit;
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}
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//cyclesForBit -= cyclesPerBit;
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//cyclesLeftForBit = ceil(cyclesPerBit - cyclesForBit);
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//cyclesForBit += cyclesLeftForBit;
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if (GetNextBit())
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{
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ResetEncoderDecoder(18 * 16, /*20 * 16*/ 2 * 16);
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}
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}
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if (fluxReversalCyclesLeft == 0)//Not entirely right, a flux reversal will be skipped if a bit read was going to happen
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{
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ResetEncoderDecoder(2 * 16, /*25 * 16*/23 * 16); // Trigger a random noise generated zero crossing and start seeing more anywhere between 2us and 25us after this one.
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}
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if (UE7Counter == 0x0) // The count carry (bit 4) clocks UF4.
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{
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UE7Counter = 16-CLOCK_SEL_AB; // A and B inputs of UE7 come from the VIA's CLOCK SEL A/B outputs (ie PB5/6) ie preload the encoder/decoder clock for the current density settings.
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// The decoder consists of UF4 and UE5A. The ecoder has two outputs, Pin 1 of UE5A is the serial data output and pin 2 of UF4 (output B) is the serial clock output.
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++UF4Counter &= 0xf; // Clock and clamp UF4.
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// The UD2 read shift register is clocked by serial clock (the rising edge of encoder/decoder's UF4 B output (serial clock))
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// - ie on counts 2, 6, 10 and 14 (2 is the only count that outputs a 1 into readShiftRegister as the MSB bits of the count NORed together for other values are 0)
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//if ((UF4Counter & 0x3) == 2)
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if (UF4Counter == 2 || UF4Counter == 6) //You'd think the bit operation should be faster...
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{
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readShiftRegister <<= 1;
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readShiftRegister |= (UF4Counter == 2); // Emulate UE5A and only shift in a 1 when pins 6 (output C) and 7 (output D) (bits 2 and 3 of UF4Counter are 0. ie the first count of the bit cell)
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writeShiftRegister <<= 1;
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// Note: SYNC can only trigger during reading as R/!W line is one of UC2's inputs.
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if (((readShiftRegister & 0x3ff) == 0x3ff)) // if the last 10 bits are 1s then SYNC
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{
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UE3Counter = 0; // Phase lock on to byte boundary
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m_pVIA->GetPortB()->SetInput(0x80, false); // PB7 active low SYNC
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}
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else
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{
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m_pVIA->GetPortB()->SetInput(0x80, true); // SYNC not asserted if not following the SYNC bits
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UE3Counter++;
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}
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}
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// UC5B (NOR used to invert UF4's output B serial clock) output high when UF4 counts 0,1,4,5,8,9,12 and 13
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else if (((UF4Counter & 2) == 0) && (UE3Counter == 8)) // Phase locked on to byte boundary
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{
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UE3Counter = 0;
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SO = (m_pVIA->GetFCR() & m6522::FCR_CA2_OUTPUT_MODE0) != 0; // bit 2 of the FCR indicates "Byte Ready Active" turned on or not.
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writeShiftRegister = (u8)(readShiftRegister & 0xff);
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m_pVIA->GetPortA()->SetInput(writeShiftRegister);
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}
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}
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};
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}
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void Drive::DriveLoopWrite()
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{
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const unsigned int cycleStep = 16 - CLOCK_SEL_AB;
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unsigned int cycles = 16 - UE7Counter;
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while(cycles < 16)
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unsigned int cycles = 16;
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while(true)
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{
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//No check is required. This loops is all about the UE7Counter.
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//if (UE7Counter == 0x10) // The count carry (bit 4) clocks UF4.
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if (cycles < UE7Counter)
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{
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UE7Counter = CLOCK_SEL_AB; // A and B inputs of UE7 come from the VIA's CLOCK SEL A/B outputs (ie PB5/6) ie preload the encoder/decoder clock for the current density settings.
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UE7Counter -= cycles;
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cycles = 0;
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return;
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}
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cycles -= UE7Counter;
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UE7Counter = 16 - CLOCK_SEL_AB; // A and B inputs of UE7 come from the VIA's CLOCK SEL A/B outputs (ie PB5/6) ie preload the encoder/decoder clock for the current density settings.
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// The decoder consists of UF4 and UE5A. The ecoder has two outputs, Pin 1 of UE5A is the serial data output and pin 2 of UF4 (output B) is the serial clock output.
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++UF4Counter &= 0xf; // Clock and clamp UF4.
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// The UD2 read shift register is clocked by serial clock (the rising edge of encoder/decoder's UF4 B output (serial clock))
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@ -681,15 +886,6 @@ void Drive::DriveLoopWrite()
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SO = (m_pVIA->GetFCR() & m6522::FCR_CA2_OUTPUT_MODE0) != 0; // bit 2 of the FCR indicates "Byte Ready Active" turned on or not.
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writeShiftRegister = m_pVIA->GetPortA()->GetOutput();
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}
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if ((16-cycles) < cycleStep)
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{
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UE7Counter += 16 - cycles;
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return;
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}
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}
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UE7Counter += cycleStep;
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cycles += cycleStep;
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}
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}
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#endif
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@ -51,6 +51,9 @@ public:
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#if defined(EXPERIMENTALZERO)
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void DriveLoopWrite();
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void DriveLoopRead();
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void DriveLoopReadNoFluxNoCycles();
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void DriveLoopReadNoFlux();
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void DriveLoopReadNoCycles();
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#endif
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void Insert(DiskImage* diskImage);
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@ -69,7 +72,7 @@ private:
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int32_t localSeed;
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inline void ResetEncoderDecoder(unsigned int min, unsigned int /*max*/span)
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{
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UE7Counter = CLOCK_SEL_AB; // A and B inputs of UE7 come from the VIA's CLOCK SEL A/B outputs (ie PB5/6)
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UE7Counter = 16 - CLOCK_SEL_AB; // A and B inputs of UE7 come from the VIA's CLOCK SEL A/B outputs (ie PB5/6)
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UF4Counter = 0;
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localSeed = ((localSeed * 1103515245) + 12345) & 0x7fffffff;
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fluxReversalCyclesLeft = (span) * (localSeed >> 11) + min;
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@ -93,6 +93,7 @@ extern u16 pc;
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u8 read6502_1581(u16 address)
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{
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u8 value = 0;
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#if not defined(EXPERIMENTALZERO)
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if (address & 0x8000)
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{
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value = roms.Read1581(address);
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@ -115,6 +116,7 @@ u8 read6502_1581(u16 address)
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{
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value = address >> 8; // Empty address bus
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}
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#endif
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return value;
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}
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@ -127,6 +129,7 @@ u8 peek6502_1581(u16 address)
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void write6502_1581(u16 address, const u8 value)
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{
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#if not defined(EXPERIMENTALZERO)
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if (address & 0x8000)
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{
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return;
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@ -145,6 +148,7 @@ void write6502_1581(u16 address, const u8 value)
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{
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s_u8Memory[address & 0x1fff] = value;
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}
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#endif
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}
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static void CIAPortA_OnPortOut(void* pUserData, unsigned char status)
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@ -277,7 +277,7 @@ public:
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RPI_SetGpioPinFunction((rpi_gpio_pin_t)PIGPIO_OUT_SRQ, FS_OUTPUT);
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}
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#if not defined(EXPERIMENTALZERO)
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// Set up audio.
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write32(CM_PWMDIV, CM_PASSWORD + 0x2000);
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write32(CM_PWMCTL, CM_PASSWORD + CM_ENAB + CM_SRC_OSCILLATOR); // Use Default 100MHz Clock
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@ -285,7 +285,7 @@ public:
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write32(PWM_RNG1, 0x1B4); // 8bit 44100Hz Mono
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write32(PWM_RNG2, 0x1B4);
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write32(PWM_CTL, PWM_USEF2 + PWM_PWEN2 + PWM_USEF1 + PWM_PWEN1 + PWM_CLRF1);
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#endif
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int buttonCount = sizeof(ButtonPinFlags) / sizeof(unsigned);
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for (index = 0; index < buttonCount; ++index)
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27
src/main.cpp
27
src/main.cpp
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@ -101,7 +101,9 @@ u8 s_u8Memory[0xc000];
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int numberOfUSBMassStorageDevices = 0;
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DiskCaddy diskCaddy;
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Pi1541 pi1541;
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#if not defined(EXPERIMENTALZERO)
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Pi1581 pi1581;
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#endif
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CEMMCDevice m_EMMC;
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Screen screen;
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ScreenLCD* screenLCD = 0;
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@ -118,8 +120,9 @@ bool USBKeyboardDetected = false;
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bool selectedViaIECCommands = false;
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u16 pc;
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#if not defined(EXPERIMENTALZERO)
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SpinLock core0RefreshingScreen;
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|
||||
#endif
|
||||
unsigned int screenWidth = 1024;
|
||||
unsigned int screenHeight = 768;
|
||||
|
||||
|
|
@ -609,6 +612,7 @@ EmulatingMode BeginEmulating(FileBrowser* fileBrowser, const char* filenameForIc
|
|||
DiskImage* diskImage = diskCaddy.SelectFirstImage();
|
||||
if (diskImage)
|
||||
{
|
||||
#if not defined(EXPERIMENTALZERO)
|
||||
if (diskImage->IsD81())
|
||||
{
|
||||
pi1581.Insert(diskImage);
|
||||
|
|
@ -617,6 +621,7 @@ EmulatingMode BeginEmulating(FileBrowser* fileBrowser, const char* filenameForIc
|
|||
return EMULATING_1581;
|
||||
}
|
||||
else
|
||||
#endif
|
||||
{
|
||||
pi1541.drive.Insert(diskImage);
|
||||
fileBrowser->DisplayDiskInfo(diskImage, filenameForIcon);
|
||||
|
|
@ -668,7 +673,9 @@ void GlobalSetDeviceID(u8 id)
|
|||
deviceID = id;
|
||||
m_IEC_Commands.SetDeviceId(id);
|
||||
pi1541.SetDeviceID(id);
|
||||
#if not defined(EXPERIMENTALZERO)
|
||||
pi1581.SetDeviceID(id);
|
||||
#endif
|
||||
}
|
||||
|
||||
void CheckAutoMountImage(EXIT_TYPE reset_reason , FileBrowser* fileBrowser)
|
||||
|
|
@ -712,10 +719,6 @@ EXIT_TYPE Emulate1541(FileBrowser* fileBrowser)
|
|||
if (numberOfImagesMax > 10)
|
||||
numberOfImagesMax = 10;
|
||||
|
||||
core0RefreshingScreen.Acquire();
|
||||
diskCaddy.Display();
|
||||
core0RefreshingScreen.Release();
|
||||
|
||||
inputMappings->directDiskSwapRequest = 0;
|
||||
// Force an update on all the buttons now before we start emulation mode.
|
||||
IEC_Bus::ReadBrowseMode();
|
||||
|
|
@ -731,8 +734,6 @@ EXIT_TYPE Emulate1541(FileBrowser* fileBrowser)
|
|||
pi1541.Reset(); // will call IEC_Bus::Reset();
|
||||
IEC_Bus::OutputLED = false;
|
||||
IEC_Bus::LetSRQBePulledHigh();
|
||||
float avgTimer = 0.0f;
|
||||
|
||||
ctBefore = read32(ARM_SYSTIMER_CLO);
|
||||
|
||||
//resetWhileEmulating = false;
|
||||
|
|
@ -756,7 +757,6 @@ EXIT_TYPE Emulate1541(FileBrowser* fileBrowser)
|
|||
}
|
||||
bool buttonState = false;
|
||||
bool prevButtonState = false;
|
||||
|
||||
while (true)
|
||||
{
|
||||
|
||||
|
|
@ -1274,8 +1274,9 @@ void emulator()
|
|||
IEC_Bus::Reset();
|
||||
|
||||
IEC_Bus::LetSRQBePulledHigh();
|
||||
|
||||
#if not defined(EXPERIMENTALZERO)
|
||||
core0RefreshingScreen.Acquire();
|
||||
#endif
|
||||
IEC_Bus::WaitMicroSeconds(100);
|
||||
|
||||
roms.ResetCurrentROMIndex();
|
||||
|
|
@ -1285,9 +1286,9 @@ void emulator()
|
|||
fileBrowser->ClearSelections();
|
||||
|
||||
fileBrowser->RefeshDisplay(); // Just redisplay the current folder.
|
||||
|
||||
#if not defined(EXPERIMENTALZERO)
|
||||
core0RefreshingScreen.Release();
|
||||
|
||||
#endif
|
||||
selectedViaIECCommands = false;
|
||||
|
||||
inputMappings->Reset();
|
||||
|
|
@ -1590,7 +1591,7 @@ static void CheckOptions()
|
|||
|
||||
deviceID = (u8)options.GetDeviceID();
|
||||
DEBUG_LOG("DeviceID = %d\r\n", deviceID);
|
||||
|
||||
#if not defined(EXPERIMENTALZERO)
|
||||
const char* FontROMName = options.GetRomFontName();
|
||||
if (FontROMName)
|
||||
{
|
||||
|
|
@ -1625,7 +1626,7 @@ static void CheckOptions()
|
|||
//DEBUG_LOG("Read ROM %s from options\r\n", ROMName);
|
||||
}
|
||||
}
|
||||
|
||||
#endif
|
||||
const char* ROMName1581 = options.GetRomName1581();
|
||||
if (ROMName1581)
|
||||
{
|
||||
|
|
|
|||
Loading…
Reference in a new issue