32 lines
738 B
C
32 lines
738 B
C
// Part of PiTubeDirect
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// https://github.com/hoglet67/PiTubeDirect
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// cache.h
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#ifndef CACHE_H
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#define CACHE_H
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// Memory below 64MB is L1 and L2 cached (inner and outer)
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// Mark the memory above 64MB to 128MB as L2 cached only (outer)
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#define L2_CACHED_MEM_BASE 0x04000000
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// Mark the memory above 128MB as uncachable
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#define UNCACHED_MEM_BASE 0x08000000
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// Location of the high vectors (last page of L1 cached memory)
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#define HIGH_VECTORS_BASE (L2_CACHED_MEM_BASE - 0x1000)
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// The first 2MB of memory is mapped at 4K pages so the 6502 Co Pro
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// can play tricks with banks selection
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#define NUM_4K_PAGES 512
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#ifndef __ASSEMBLER__
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void map_4k_page(int logical, int physical);
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void enable_MMU_and_IDCaches(void);
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#endif
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#endif
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