128 lines
3.3 KiB
C
128 lines
3.3 KiB
C
//
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// synchronize.c
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//
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// USPi - An USB driver for Raspberry Pi written in C
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// Copyright (C) 2014-2015 R. Stange <rsta2@o2online.de>
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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#include <uspi/synchronize.h>
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#include <uspi/types.h>
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#include <uspi/assert.h>
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#define EnableInterrupts() __asm volatile ("cpsie i")
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#define DisableInterrupts() __asm volatile ("cpsid i")
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static volatile unsigned s_nCriticalLevel = 0;
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static volatile boolean s_bWereEnabled;
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void uspi_EnterCritical (void)
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{
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u32 nFlags;
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asm volatile ("mrs %0, cpsr" : "=r" (nFlags));
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DisableInterrupts ();
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if (s_nCriticalLevel++ == 0)
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{
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s_bWereEnabled = nFlags & 0x80 ? FALSE : TRUE;
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}
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DataMemBarrier ();
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}
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void uspi_LeaveCritical (void)
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{
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DataMemBarrier ();
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assert (s_nCriticalLevel > 0);
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if (--s_nCriticalLevel == 0)
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{
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if (s_bWereEnabled)
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{
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EnableInterrupts ();
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}
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}
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}
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#if RASPPI == 1
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//
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// Cache maintenance operations for ARMv6
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//
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// NOTE: The following functions should hold all variables in CPU registers. Currently this will be
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// ensured using maximum optimation (see circle/synchronize.h).
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//
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// The following numbers can be determined (dynamically) using CTR.
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// As long we use the ARM1176JZF-S implementation in the BCM2835 these static values will work:
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//
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#define DATA_CACHE_LINE_LENGTH 32
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void uspi_CleanAndInvalidateDataCacheRange (u32 nAddress, u32 nLength)
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{
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nLength += DATA_CACHE_LINE_LENGTH;
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while (1)
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{
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asm volatile ("mcr p15, 0, %0, c7, c14, 1" : : "r" (nAddress) : "memory");
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if (nLength < DATA_CACHE_LINE_LENGTH)
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{
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break;
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}
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nAddress += DATA_CACHE_LINE_LENGTH;
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nLength -= DATA_CACHE_LINE_LENGTH;
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}
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}
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#else
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//
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// Cache maintenance operations for ARMv7-A
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//
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// See: ARMv7-A Architecture Reference Manual, Section B4.2.1
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//
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// NOTE: The following functions should hold all variables in CPU registers. Currently this will be
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// ensured using the register keyword and maximum optimation (see uspi/synchronize.h).
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//
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// The following numbers can be determined (dynamically) using CTR, CSSELR, CCSIDR and CLIDR.
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// As long we use the Cortex-A7 implementation in the BCM2836 or the Cortex-A53 implementation
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// in the BCM2837 these static values will work:
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//
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#define L1_DATA_CACHE_LINE_LENGTH 64
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#define L2_CACHE_LINE_LENGTH 64
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#define DATA_CACHE_LINE_LENGTH_MIN 64 // min(L1_DATA_CACHE_LINE_LENGTH, L2_CACHE_LINE_LENGTH)
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void uspi_CleanAndInvalidateDataCacheRange (u32 nAddress, u32 nLength)
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{
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nLength += DATA_CACHE_LINE_LENGTH_MIN;
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while (1)
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{
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__asm volatile ("mcr p15, 0, %0, c7, c14, 1" : : "r" (nAddress) : "memory"); // DCCIMVAC
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if (nLength < DATA_CACHE_LINE_LENGTH_MIN)
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{
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break;
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}
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nAddress += DATA_CACHE_LINE_LENGTH_MIN;
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nLength -= DATA_CACHE_LINE_LENGTH_MIN;
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}
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}
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#endif
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